1. Field of the Invention
The present invention relates generally to a method for forming a plug metal layer, and in particular to a method for forming a plug tungsten (W) layer.
2. Description of the Prior Art
As semiconductor devices, such as Metal-Oxide-Semiconductor devices, become highly integrated, the area occupied by the device shrinks, as well as the design rule. With advances in semiconductor technology, the dimensions of the integrated circuit (IC) devices have shrunk to the deep sub-micron range. When the semiconductor device continuously shrinks to the deep sub-micron region, some problems described below are incurred due to the scaling down process.
Generally known in the art of integrated circuit fabrication is the use of titanium nitride layers. Titanium nitride layers within integrated circuit fabrication are most commonly employed as either barrier layers or adhesion promoter layers. When employed as barrier layers, titanium nitride layers are typically formed interposed between a conductor metallization layer and a doped silicon layer or a doped silicon semiconductor substrate. When formed in this location, a titanium nitride layer provides a barrier to inhomogeneous inter-diffusion and spiking from the conductor metallization layer into the doped silicon layer or the doped silicon semiconductor substrate. Titanium nitride layers, which are employed as barrier layers, are particularly well evolved within integrated circuit fabrication. Alternatively, when employed as adhesion promoter layers, titanium nitride layers within integrated circuits are typically formed as liner layers beneath blanket tungsten layers from which in turn are formed conductive contact and interconnection studs through patterned dielectric layers within those integrated circuits.
While the barrier layer characteristics of titanium nitride layers have made titanium nitride layers quite common within integrated circuit fabrication, methods through which such titanium nitride layers may be formed within integrated circuits are not entirely without problems. In particular, within the titanium nitride layers the integrated circuit device dimensions have decreased, and the aspect ratios of apertures has increased within those integrated circuits. It has become increasingly difficult to form, through conventional physical vapor deposition (PVD) sputtering methods, titanium nitride layers with adequate step coverage. The difficulty derives from the inherent line-of-sight deposition characteristics of conventional physical vapor deposition (PVD) sputtering methods employed in forming integrated circuit layers of titanium nitride, as well as other materials. The line-of-sight deposition characteristics typically provide only limited sidewall and bottom coverage of titanium nitride within a narrow high aspect ratio aperture (i.e., an aperture with a width less than about 0.5 microns and an aspect ratio greater than about 3). A titanium nitride layer is desired in comparison with titanium nitride coverage upon the surface of the integrated circuit layer (typically a dielectric layer) within which is formed the aperture.
In response to the step coverage limitations inherent in forming titanium nitride layers through physical vapor deposition (PVD) sputtering methods, there has alternatively been proposed and disclosed the use of chemical vapor deposition (CVD) methods for forming titanium nitride layers within integrated circuits. Titanium nitride layers formed through chemical vapor deposition (CVD) methods have inherently superior step coverage within narrow high aspect ratio apertures within integrated circuits since chemical vapor deposition (CVD) methods, in general, proceed through a surface diffusion deposition phenomenon rather than a line-of-sight deposition phenomenon.
Chemical vapor deposition (CVD) methods may be employed within integrated circuits to provide titanium nitride layers with superior step coverage for narrow high aspect ratio apertures. Chemical vapor deposition (CVD) methods are also not entirely without problems when forming titanium nitride layers within integrated circuits with optimally desirable properties. In that regard, it is difficult to deposit titanium nitride layers at comparatively low temperatures (i.e., less than a temperature of about 550 degrees centigrade at which aluminum containing conductor metallization layers deteriorate) through low pressure chemical vapor deposition (LPCVD) methods. Simultaneously, it is also difficult to deposit titanium nitride layers with a low resistivity and impurity concentration through metal organic chemical vapor deposition (MOCVD) methods. Particularly undesirable impurities formed within titanium nitride layers deposited through metal organic chemical vapor deposition (MOCVD) methods are carbon, oxygen, and hydrogen. These impurities increase the difficulty of the subsequent process, for example, a gap fill process.
In general, a titanium layer and a titanium nitride layer are first formed to form a barrier layer in the process for forming a plug tungsten layer. Next, the titanium nitride layer is treated by way of using a plasma process, and then the tungsten process is performed. Nevertheless, there is the directional issue when the conventional plasma process for the treatment of the barrier layer is used to treat the surface of the barrier layer in the via hole. That is, the treatment of the conventional plasma process cannot overall suffuse the barrier layer and, hence, the resulting treatment of the titanium nitride layer on the sidewall of the via hole is incomplete. Furthermore, if the titanium nitride layer is formed by way of metal organic chemical vapor deposition (MOCVD), the titanium nitride layer on the sidewall of the via hole without plasma will have residual volatility solvent therein, therefore causing xe2x80x9cout-gassing.xe2x80x9d
The issues above result from the most commonly used precursors for metal organic chemical vapor deposition (MOCVD) which are TDMAT and TDEAT, and which might end up with a TiN layer having carbon and/or hydrogen byproducts after a thermal dissociation process. A conventional method used in solving the above problem is to use nitrogen (N2) and/or hydrogen (H2) plasma treatment to reduce the byproduct content within the TiN layer, as well as reducing its resistivity and water absorption.
Nevertheless, anisotropic plasma treatment against deeper trenches, that is, trenches having high aspect ratios, cannot effectively remove the residing byproducts in the sidewalls of the via/contact holes. Thus, the byproduct contents at the sidewall and at the top of the via/contact holes are very different, which result in different metal deposition rates over the treated/untreated TiN barrier layer at later stages, that is, selectivity of the metal chemical vapor deposition. As shown in FIG. 1, the selectivity of the metal chemical vapor deposition is a ratio of the thickness of the metal nucleation, wherein the ratio (b/a) is the thickness of the metal nucleation on the top of the via hole (with the treatment of plasma) and the sidewall of the via hole (without the treatment of plasma). In the conventional process for the metal chemical vapor deposition, the ratio of b to a is about 40 to 60% or 50 to 70% that is due to the fact that the sidewall of the via hole cannot be treated with the plasma process and, hence, discontinuous and insufficient nucleation sites.
In such a situation, the side-wall deposition rate is less than the top deposition rate, as the plug metal is laid down, it tends to cover the via/contact holes before the metal layer covering the opposite sides of the holes meets. This forms an open area in the holes called a xe2x80x9cseamxe2x80x9d phenomena. When the plug metal layer etch back is performed, the void is opened, which forms an irregular upper surface on the metal plug in the well. It is very difficult to form a good contact between the irregular upper surface of the open via/contact plug and the interconnect line. Metal applied to such irregular surfaces tends to crack or break over time, such as an over-high resistance constant (RC), which can cause a defective integrated circuit and can create major reliability problems. Especially for device generation smaller than 0.18 micrometer, the process integration is very difficult owing to the resistance constant (RC) being too high and, hence, unstable.
In accordance with the above description, a new and improved method for forming a plug metal layer is therefore necessary so as to raise the yield and quality of the follow-up process.
In accordance with the present invention, a method is provided for forming a plug metal layer that substantially overcomes the drawbacks of the above mentioned problems that arise from conventional methods.
Accordingly, it is a main object of the present invention to provide a method for forming a plug metal layer. This invention can perform the cycle step of an atomic layer deposition (ALD) to form a continuous metal seed layer (CMSL), so as to raise the selectivity of the metal. Furthermore, the steps of the atomic layer deposition (ALD) of the present invention is to individually transport the reactive gas in order to prevent the issue of competitive adsorption whereby a thin continuous metal seed layer (CMSL ) with continuous and dense nucleation sites is formed. The thickness of the continuous metal seed layer (CMSL) is only about 20 to 40 xc3x85, wherein the thin continuous metal seed layer (CMSL) can substitute for the thick nucleation layer that is about more than 500 xc3x85. It is necessary to be formed in the conventional process, because the nucleation sites are insufficient. Moreover, the continuous metal seed layer (CMSL) also can be reformed before the nucleation layer is formed to reduce the thickness of the nucleation layer, and this can make for a better gap-filling process. Therefore, the present invention makes cost reductions that correspond to a positive economic effect and are appropriate for deep sub-micron technology.
In accordance with the present invention, a new process for forming a plug metal layer is disclosed. First of all, a semiconductor substrate is provided. Then a dielectric layer is deposited on the semiconductor substrate. Next, forming and defining a photoresist layer on the dielectric layer. An etching process is then performed by the photoresist layer as an etched mask to form a via hole. After removing the photoresist layer, a barrier layer on the dielectric layer and the sidewall and bottom of the via hole is formed. Afterward, the barrier layer is treated by way of a plasma process. Subsequently, the formation of an atomic layer deposition (ALD) at least once is performed to form a continuous metal seed layer (CMSL) on the barrier layer, wherein the atomic layer deposition comprises: a mixing gas of hydrogen and silane, such as hydroxy silane or tetrahydroxy silane, is transported on the barrier layer. Next, a purge/vacuum process is performed. Then a reactive gas, such as WF6, is transported to form the continuous metal seed layer (CMSL). The cycle step of the atomic layer deposition (ALD) can be repeated to form the thickness of the continuous metal seed layer (CMSL) about 20 to 40 xc3x85. Then a nucleation layer is formed on the continuous metal seed layer (CMSL). Afterward, a blanket metal layer is formed on the nucleation layer. Finally, the blanket metal layer is etched back by way of a chemical mechanical polishing process (CMP) and a plug metal layer is formed on the via hole.